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ml60851a ? semiconductor 1/44 general description the ml60851a is a general purpose universal serial bus (usb) device controller. the ml60851a provides a usb interface, control/status block, application interface, and fifos. the fifo interface and two types of transfer have been optimized for bulkout devices such as printers and bulkin devices such as digital still cameras and image scanners. in addition, mass storage devices are also applicable to this device. features ? usb 1.0 compliant ? built-in usb transceiver circuit ? full-speed (12 mb/sec) support ? supports printer device class, image device class, and mass storage device class ? supports three types of transfer; control transfer, bulk transfer, and interrupt transfer ? built-in fifos for control transfer two 8-byte fifos (one for receive fifo and the other for transmit fifo) ? built-in fifos for bulk transfer (available for either receive fifo or transmit fifo) one 64-byte fifo two 64-byte fifos ? built-in fifo for interrupt transfer one 8-byte fifo ? supports one control endpoint, two bulk endpoint addresses, and one interrupt endpoint address ? two 64-byte fifos enable fast bulkout transfer and bulkin transfer ? supports 8 bit/16 bit dma transfer ?v cc is 3.0 v to 3.6 v ? supporting dual power supply enables 5 v application interface ? built-in 48 mhz oscillator circuit ? package options: 44-pin plastic qfp (qfp44-p-910-0.80-2k) (product name: ml60851aga) 44-pin plastic tqfp (tqfp44-p-1010-0.80-k) (product name: ML60851ATB) ? semiconductor ml60851a usb device controller e2n0026-18-y3 this version: nov. 1998 preliminary
ml60851a ? semiconductor 2/44 block diagram 48 mhz xin xout d+ dC usb bus oscillator usb transceiver dpll protocol engine status/control endpoint fifo/ 8-byte setup register application interface application module (local mcu) a7:a0 d15:d0 cs , wr , rd reset intr dreq dack ml60851a
ml60851a ? semiconductor 3/44 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 d+ de v cc3 test1 test2 xin xout cs rd wr reset intr d15 d14 d13 d12 v ss v cc5 d11 d10 d9 d8 ale adsel a7 a6 a5 a4 a3 a2 a1 a0 dack dreq ad7 ad6 ad5 ad4 v ss v cc5 ad3 ad2 ad1 ad0 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 44-pin plastic tqfp 44-pin plastic qfp 1 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 d+ de v cc3 test1 test2 xin xout cs rd wr reset intr d15 d14 d13 d12 v ss v cc5 d11 d10 d9 d8 ale adsel a7 a6 a5 a4 a3 a2 a1 a0 dack dreq ad7 ad6 ad5 ad4 v ss v cc5 ad3 ad2 ad1 ad0 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22
ml60851a ? semiconductor 4/44 pin description pin 1, 2 6, 7 13 to 16, 19 to 22 35 to 38, 41 to 44 25 to 32 8 9 10 12 34 33 23 24 11 symbol type i/o i/o i/o i i i i o o i i i i description d+, dC usb data pin for external crystal oscillator data bus (msb) data bus (lsb)/address input address input chip select signal input pin. low active read signal input pin. low active write signal input pin. low active interrupt request signal output pin dma request output pin dma acknowledge signal input pin address latch enable signal input pin address input mode select input pin. "h": address/data multiplex system reset signal input pin. low active xin, xout d15:d8 ad7:ad0 a7:a0 cs rd wr intr dreq dack ale adsel reset 4, 5 i test pins (normally "l") test1, 2
ml60851a ? semiconductor 5/44 internal registers addresses and names of registers a5:a0 a7, a6 read address a7, a6 write register name device address register device state register packet error register receive fifo register transmit fifo register endpoint packet-ready register endpoint 0 receive-byte count register endpoint 1 receive-byte count register endpoint 2 receive-byte count register flash transmit fifo system control bmrequesttype setup register brequest setup register wvalue lsb setup register wvalue msb setup register windex lsb setup register windex msb setup register wlength lsb setup register wlength msb setup register assertion select register interrupt enable register interrupt status register dma control register dma interval register endpoint 0 receive control register endpoint 0 receive general register endpoint 0 receive payload register reserved endpoint 1 control register endpoint 1 general register endpoint 1 payload register reserved 01b 01b 01b 01b 01b 01b 01b 01b 01b 01b 01b 01b 01b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 11b 00h 01h 02h 03h 04h 08h 09h 0ah 0bh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h 25h 26h 27h reserved
ml60851a ? semiconductor 6/44 addresses and names of registers (continued) endpoint 0 transmit control register endpoint 0 transmit general register endpoint 0 transmit payload register endpoint 0 general register endpoint 2 control register endpoint 2 general register endpoint 2 payload register reserved endpoint 0 receive fifo data endpoint 1 receive fifo data endpoint 0 transmit fifo data endpoint 3 transmit fifo data 01b 01b 01b 01b 01b 11b 11b 11b 11b 11b 11b 11b 11b 11b 01b 01b 30h 31h 32h 33h 34h 35h 36h 37h 00h 01h 00h 03h a5:a0 a7, a6 read address a7, a6 write register name endpoint 2 receive fifo data endpoint 1 transmit fifo data 11b 01b 02h 01h endpoint 3 payload register 01b 11b 3ah endpoint 3 general register 01b 11b 39h endpoint 3 control register 01b 11b 38h endpoint 2 transmit fifo data 11b 02h
ml60851a ? semiconductor 7/44 register description device address register (c0h, 40h) rfu d7 d6 d5 d4 d3 d2 d1 d0 device address (r/w) the local mcu writes a device address, which is given by the set_address command form the host computer, into this register. thereafter, this device processes an only token packet transmitted to the given device address. device state register (c1h, 41h) rfu d7 d6 d5 d4 d3 d2 d1 d0 default state (r/w) address state (r/w) configuration state (r/w) suspended state (r) usb bus reset clear ( w ) remote wakeup (r/w) default, address, and configuration states: d2, d1, and d0 are set to 0, 0, and 1 (default states) by reset respectively. changing the values of this register gives no influence on operation of this device. suspended state: this register is asserted when the device enters the suspended state. this register is deaserted by reset or when the device exits the suspended state by a resume signaling from the usb bus. remote wakeup: when this device signals a remote wakeup during the suspended state, this register is asserted by a local mcu. this register is automatically deasserted when the device exits the suspended state by a resume signaling from the usb bus. usb bus reset status clear: writing "1" to this bit causes the interrupt status to be cleared (the usb bus reset interrupt status bit is "0" and the intr pin is deasserted) while the usb bus reset interrupt is being serviced (when d5, the usb bus reset interrupt status bit, of the interrupt status register is "1" and the intr pin is asserted). this bit is readable, and when read, its value will be always "0". packet error register (c2h, C) rfu d7 d6 d5 d4 d3 d2 d1 d0 bit stuff error (r) data crc error (r) address crc error (r) pid error (r) rfu = 0000b
ml60851a ? semiconductor 8/44 fifo status register 1 (c3h, C) rfu d7 d6 d5 d4 d3 d2 d1 d0 receive fifo0 full (r) receive fifo0 empty (r) fifo1 full (r) fifo1 em p t y ( r ) rfu = 0000b fifo status register 2 (c4h, C) rfu d7 d6 d5 d4 d3 d2 d1 d0 transmit fifo0 full (r) transmit fifo0 empty (r) fifo2 full (r) fifo2 empty (r) rfu = 0000b fifo3 full (r) fifo3 em p t y ( r ) endpoint packet-ready register (c8h, 48h) d7 d5 d4 d3 d2 d1 d0 d6 rfu ep0 receive packet ready (r/reset) ep1 receive packet ready (r/reset) ep0 transmit packet ready (r/set) ep1 transmit packet ready (r/set) ep2 receive packet ready (r/reset) ep3 transmit packet ready ( r/set ) ep2 transmit packet ready (r/set) receive packet ready: when a valid packet arrives at an endpoint, this bit is automatically set and the endpoint is locked. when "1" is written in this register, receiver packet ready is reset and the endpoint is unlocked. (this bit also is set to "0".) when dma is enabled, ep1 receive packet ready is automatically reset after all the data in ep1 is read during dma transfer. transmit packet ready: when "1" is written in this register, the transmit packet ready is set and the packet in the corresponding endpoint is transmitted. transmit packet ready is automatically reset when the ack handshake is returned from the host. when dma is enabled, ep1 transmit packet ready is automatically set after the data written in ep1 reaches the maximum packet size during dma transfer. the value of this register remains unchanged when "0" is written in this register.
ml60851a ? semiconductor 9/44 endpoint 0 receive byte count register (c9h, C) rfu d7 d6 d5 d4 d3 d2 d1 d0 ep0 byte count (r) rfu d7 d6 d5 d4 d3 d2 d1 d0 ep1 byte count (r) endpoint 1 receive byte count register (cah, C) rfu d7 d6 d5 d4 d3 d2 d1 d0 ep2 byte count (r) endpoint 2 receive byte count register (cbh, C) flash transmit fifo (C, 4eh) system control (C, 4fh) 0 d7 d6 d5 d4 d2 d1 d0 d3 00 0 0 in case ep1 is set as a transmission endpoint, when "1" is written in this bit, the fifo at ep1 is cleared and packet ready at ep1 is reset by the write pulse. in case ep2 is set as a transmission endpoint, when "1" is written in this bit, the fifo at ep2 is cleared and packet ready at ep2 is reset by the write pulse. in case ep3 is set as a transmission endpoint, when "1" is written in this bit, the fifo at ep3 is cleared and packet read y at ep3 is reset b y the write p ulse. d7 d6 d5 d4 d2 d1 d0 d3 0 0 when "1" is written in this bit, the ml60851a is reset by the write pulse. 0 oscillation sto p command oscillation stop command: writing 1010b to d7 to d4, (writing a0h into this register) causes the oscillator circuit of the ml60851a to be deactivated and go into the standby mode. when oscillation is stopped, reading and writing into the register is possible but reading and writing into fifo is not possible. asserting the reset pin restarts oscillation. note: please clear all fifos at the same time, otherwise some of them may not be cleared.
ml60851a ? semiconductor 10/44 bmrequesttype setup register (d0h, C) type (r) 0 = device 1 = interface 2 = endpoint 3 = others 4 to 31 = reserved 0 = standard 1 = class 2 = vendor 3 = reserved 0 = host to device 1 = device to host data transfer direction (r) recipient (r) d7 d6 d5 d4 d2 d1 d0 d3 brequest setup register (d1h, C) d7 d6 d5 d4 d2 d1 d0 d3 specific request (r) ? wvaluelsb setup register (d2h, C) d7:d0 = lsb of word size field (r) ? wvaluemsb setup register (d3h, C) d7:d0 = msb of word size field (r) ? windexlsb setup register (d4h, C) d7:d0 = lsb of word size field (r) ? windexmsb setup register (d5h, C) d7:d0 = msb of word size field (r) ? wlengthlsb setup register (d6h, C) this field defines the length of data that is transferred in the second stage (data stage) of control transfer. (r) ? wlengthmsb setup register (d7h, C) this field defines the length of data that is transferred in the data stage of control transfer. (r)
ml60851a ? semiconductor 11/44 assertion select register (dah, 5ah) (r/w) rfu d7 d6 d5 d4 d3 d2 d1 d0 0 = active low (initial value) 1 = active high assertion of dack assertion of dreq assertion of intr 0 = active low (initial value) 1 = active high 0 = active high (initial value) 1 = active low interrupt enable register (dbh, 5bh) (r/w) d7 d6 d5 d4 d3 d2 d1 d0 setup ready interrupt enable ep1 packet ready interrupt enable ep2 packet ready interrupt enable ep0 receive packet ready interrupt enable ep0 transmit packet ready interrupt enable suspended state interrupt enable usb bus reset interrupt enable ep3 packet ready interrupt enable initial value of d0 is 1. initial values of d1 to d7 are 0.
ml60851a ? semiconductor 12/44 interrupt status register (dch, 5ch) (r) d7 d6 d5 d4 d3 d2 d1 d0 setup ready interrupt status (r) ep1 packet ready interrupt status (r) ep2 packet ready interrupt status (r) ep0 receive packet ready interrupt status (r) ep0 transmit packet ready interrupt status (r) suspended state interrupt status (r) usb bus reset interrupt status ep3 packet ready interru p t status setup ready interrupt status: equivalent to setup ready at (f3h) described later when the corresponding interrupt enable bit is asserted. ep1 packet ready interrupt status: equivalent to ep1 receive packet ready (the complement of ep1 transmit packet ready when ep1 is set for transmitter) at (c8h) described before when the corresponding interrupt enable bit is asserted. ep2 packet ready interrupt status: equivalent to ep2 receive packet ready (the complement of ep2 transmit packet ready when ep2 is set for transmitter) at (c8h) described before when the corresponding interrupt enable bit is asserted. ep0 receive packet ready interrupt status: equivalent to ep0 receive packet ready at (c8h) described before when the corresponding interrupt enable bit is asserted. ep0 transmit packet ready interrupt status: equivalent to the complement of ep0 transmit packet ready at (c8h) described before when the corresponding interrupt enable bit is asserted. usb bus reset interrupt status: this bit is set to "1" at usb bus reset when the d5 bit of the interrupt enable register (dbh) is "1". to return this bit back to "0", "1" should be written to the d5 bit of the device states register. suspended state interrupt status: equivalent to suspended state register at (c1h) described before when the corresponding interrupt enable bit is asserted. ep3 packet ready interrupt status: when the d7 bit of the interrupt enable register (dbh) is "1", the complement of the d7 bit of the endpoint packet ready register (c8h) is being copied.
ml60851a ? semiconductor 13/44 dma control register (ddh, 5dh) (r/w) rfu d7 d6 d5 d4 d3 d2 d1 d0 0 = disables dma transfer (initial value) 1 = enables dma transfer for ep1 0 = single address mode (initial value) 1 = dual address mode 0 = (initial value) 1 = inserts ep1 receive byte count into the top byte or top word of the transfer data. (note 1) 0 = byte (8 bits) (initial value) 1 = word (16 bits) (note 2) 0 = single transfer mode (initial value) 1 = demand transfer mode transfer mode transfer size byte count address mode dma enable (note 1) when 16-bit mode is set, the upper byte of the top word is 00h. (note 2) w hen 16-bit mode is set and the packet size is an odd-number byte, the upper byte of the last word is 00h. dma interval register (deh, 5eh) (r/w) d7 d6 d5 d4 d3 d2 d1 d0 this register specifies a dma transfer interval between de-assertion and re-assertion of dreq in single transfer mode. the interval is specified between 0 and 255 (bit times). the initial value is 0. 1-bit time = 1/12 mhz (= 84 ns)
ml60851a ? semiconductor 14/44 endpoint 0 receive control register (e0h, C) rfu d7 d6 d5 d4 d3 d2 d1 d0 configuration bit (r) 00000rfu transfer type (r) endpoint address ( r ) configuration bit: only when this bit is asserted ("1"), a packet transmitted from a host computer to this ep is received. the packet is ignored when this bit is deasserted ("0"). this bit is deasserted by system reset and is asserted by usb reset (both d+ and d- are 0s for more than 2.5 m s). endpoint 0 receive general register (e1h, C) rfu d7 d6 d5 d4 d3 d2 d1 d0 data sequence toggle bit (r) endpoint 0 receive payload register (e2h, 62h) maximum packet size (r/w) d7 d6 d5 d4 d3 d2 d1 d0 rfu
ml60851a ? semiconductor 15/44 endpoint 1 control register (e4h, 64h) register to set the attribute of ep1. to use ep1, the local mcu writes ep1's attribute in this register by the request from the host computer. d7 d6 d5 d4 d3 d2 d1 d0 configuration bit (r/w) 00110 10 = bulk transfer endpoint address (r) stall bit (r/w) transfer type (r) 0 = reception (out endpoint) (supports printer) 1 = transmission ( in end p oint ) ( su pp orts scanner , dsc ) transfer direction (r/w) configuration bit: only when this bit is asserted ("1"), a packet transmitted from the host computer to this ep is received. the packet is ignored when this bit is deasserted ("0"). whether or not this ep is configured can be known by referencing this bit. stall bit: when this bit is asserted ("1"), a stall handshake for a packet transmitted from the host computer to this ep is automatically returned to the host computer. endpoint 1 general register (e5h, 65h) rfu d7 d6 d5 d4 d3 d2 d1 d0 data sequence toggle bit (r/reset) data sequence toggle bit: when initializing ep, pid of data0 is specified after resetting the data packet toggle bit by writing "1" to this bit (this bit goes to "0"). endpoint 1 payload register (e6h, 66h) maximum packet size (r/w) d7 d6 d5 d4 d3 d2 d1 d0 rfu
ml60851a ? semiconductor 16/44 endpoint 3 control register (f8h, 78h) register to set the attribute of ep3. to use ep3, the local mcu writes ep3's attribute in this register by the request from the host computer. configuration bit: only when this bit is asserted ("1"), a packet transmitted from the host computer to this ep is received. the packet is ignored when this bit is deasserted ("0"). whether or not this ep is configured can be known by referencing this bit. stall bit: when this bit is asserted ("1"), a stall handshake for a packet transmitted from the host computer to this ep is automatically returned to the host computer. toggle condition bit: when this bit is "0", data0 and data1 are toggled each time ack is received form the host computer by the ep3. setting this bit to "1" causes the ml60851a to go into the rate feedback mode, in which case data0 and data1 are toggled each time the packet ready is asserted by the local mcu. endpoint 3 general register (f9h, 79h) data sequence toggle bit: when initializing ep, pid of data0 is specified after resetting the data packet toggle bit by writing "1" to this bit (this bit goes to "0"). endpoint 3 payload register (fah, 7ah) d7 d6 d5 d4 d3 d2 d1 d0 configuration bit (r/w) 01111 11 = interrupt transfer endpoint address (r) stall bit (r/w) transfer type (r) 0 = number 1 = rate feedback mode toggle condition (r/w) rfu d7 d6 d5 d4 d3 d2 d1 d0 data sequence toggle bit (r/reset) maximum packet size (r/w) d7 d6 d5 d4 d3 d2 d1 d0 rfu
ml60851a ? semiconductor 17/44 endpoint 0 transmit control register (f0h, C) rfu d7 d6 d5 d4 d3 d2 d1 d0 0 0 rfu transfer t yp e ( r ) endpoint 0 transmit general register (f1h, C) rfu d7 d6 d5 d4 d3 d2 d1 d0 data sequence toggle bit (r) endpoint 0 transmit payload register (f2h, 72h) maximum packet size (r/w) d7 d6 d5 d4 d3 d2 d1 d0 rfu endpoint 0 transmit general register (f3h, 73h) rfu d7 d6 d5 d4 d3 d2 d1 d0 setup ready (r/reset) rfu stall bit (r/w) ep0 stage (r) 00 = setup stage 01 = data stage 10 = status stage setup ready: when a valid setup packet has arrived at an 8-byte setup register, this register is automatically set and the receive fifo at endpoint 0 is locked. writing "1" in this register resets setup ready. when the data stage of control write transaction follows, packet ready at endpoint 0 is also reset. therefore, the endpoint 0 receive fifo is unlocked and ready to receive the packets in the data stage. the value of this register remains unchanged when "0" is written in this register.
ml60851a ? semiconductor 18/44 endpoint 2 control register (f4h, 74h) d7 d6 d5 d4 d3 d2 d1 d0 configuration bit (r/w) 01010 10 = bulk transfer endpoint address (r) stall bit (r/w) transfer type (r) 0 = reception (out endpoint) 1 = transmission ( in end p oint ) transfer direction (r/w) configuration bit: only when this bit is asserted ("1"), a packet transmitted from the host computer to this ep is received. the packet is ignored when this bit is deasserted ("0"). whether or not this ep is configured can be known by referencing this bit. stall bit: when this bit is asserted ("1"), a stall handshake for a packet transmitted from the host computer to this ep is automatically returned to the host computer. endpoint 2 general register (f5h, 75h) rfu d7 d6 d5 d4 d3 d2 d1 d0 data sequence toggle bit (r/reset) data sequence toggle bit: when initializing ep, pid of data0 is specified after resetting the data packet toggle bit by writing "1" to this bit (this bit goes to "0"). endpoint 2 payload register (f6h, 76h) maximum packet size (r/w) d7 d6 d5 d4 d3 d2 d1 d0 rfu
ml60851a ? semiconductor 19/44 endpoint 0 receive fifo data (40h, C) area to store data to be transmitted from the host computer to this device in the data stage of control write transfer. endpoint 1 receive fifo data (41h, C) area to store data to be transmitted from the host computer to ep1 of this device in bulk out transfer. this register is valid only when ep1 is set for the out endpoint. endpoint 2 receive fifo data (42h, C) area to store data to be transmitted from the host computer to ep2 of this device in bulk out transfer. this register is valid only when ep2 is set for the out endpoint. d7 d6 d5 d4 d3 d2 d1 d0 endpoint 0 receive fifo data (r) d7 d6 d5 d4 d3 d2 d1 d0 endpoint 1 receive fifo data (r) d7 d6 d5 d4 d3 d2 d1 d0 endpoint 2 receive fifo data (r)
ml60851a ? semiconductor 20/44 endpoint 0 transmit fifo data (C, c0h) area to store data to be transmitted from this device to the host computer in the data stage of control read transter. endpoint 1 transmit fifo data (C, c1h) area to store data to be transmitted from ep1 of this device to the host computer in bulk in transfer. this register is valid only when ep1 is set for the in endpoint. endpoint 2 transmit fifo data (C, c2h) area to store data to be transmitted from ep2 of this device to the host computer in bulk in transfer. this register is valid only when ep2 is set for the in endpoint. endpoint 3 transmit fifo data (C, c3h) d7 d6 d5 d4 d3 d2 d1 d0 endpoint 0 transmit fifo data (w) d7 d6 d5 d4 d3 d2 d1 d0 endpoint 1 transmit fifo data (w) d7 d6 d5 d4 d3 d2 d1 d0 endpoint 2 transmit fifo data (w) d7 d6 d5 d4 d3 d2 d1 d0 endpoint 3 transmit fifo data (w) area to store data to be transmitted from ep3 of this device to the host computer in bulk in transfer. this register is valid only when ep3 is set for the in endpoint.
ml60851a ? semiconductor 21/44 absolute maximum ratings recommended operating conditions parameter symbol condition rating unit power supply 3 v cc3 C0.3 to +4.6 v power supply 5 v cc5 C0.5 to +6.5 v input voltage v i C0.3 to v cc5 + 0.3 v storage temperature t stg C55 to +150 c parameter symbol condition range unit power supply 3 v cc3 3.0 to 3.6 v power supply 5 v cc5 3.0 to 5.5 v operating temperature ta 0 to 70 c oscillation frequency f osc 48 mhz
ml60851a ? semiconductor 22/44 electrical characteristics dc characteristics (1) notes: 1. applied to d15:d8, ad7:ad0, a7:a0, cs , rd , wr , dack, ale, and adsel. 2. applied to xin, a7:a0, cs , rd , wr , dack, ale, and adsel. v ih = v cc3 for only xin. 3. the xin pin is fixed to high level or low level in the suspend state. all the output pins are open. parameter condition applicable pin high-level input voltage unit v max. v cc5 + 0.3 typ. min. 2.0 (v cc5 = v cc3 = 3.0 to 3.6 v, v ss = 0 v, ta = 0 to 70c) symbol v ih note 1 low-level input voltage v +0.8 C0.3 v il schmitt trigger input voltage v 2.0 1.6 v t+ reset v 1.2 0.8 v tC (v t+ ) C (v tC )v 0.4 0.1 d v t high-level output voltage i oh = C100 m av v cc5 C 0.2 v oh d15:d8 ad7:ad0 intr , dreq i oh = C4 ma v 2.4 low-level output voltage i ol = 100 m av 0.2 v ol i ol = 4 ma v 0.4 high-level input current v ih = v cc5 m a 1 0.01 i ih note 2 low-level input current v il = v ss m a C0.01 C1 i il 3-state output leakage current v oh = v cc5 m a 1 0.01 i ozh d15:d8 ad7:ad0 v ol = v ss m a C0.01 C1 i ozl power supply current (operating) ma i cc3 v cc3 power supply current (standby) note 3 m a i ccs3 v cc3 high-level input voltage v v cc3 + 0.3 v cc3 0.8 v ih xin low-level input voltage v v cc3 0.2 C0.3 v il 50 50 ma i cc5 note 3 m a i ccs5 v cc5 v cc5 5 50
ml60851a ? semiconductor 23/44 dc characteristics (2) parameter condition applicable pin high-level input voltage unit v max. v cc5 + 0.5 typ. min. 2.2 (v cc5 = 4.5 to 5.5 v, v cc3 = 3.0 to 3.6 v, v ss = 0 v, ta = 0 to 70c) symbol v ih note 1 low-level input voltage v +0.8 C0.5 v il schmitt trigger input voltage v 2.2 1.7 v t+ reset v 1.4 0.8 v tC (v t+ ) C (v tC )v 0.3 0.2 d v t high-level output voltage i oh = C100 m av v cc5 C 0.2 v oh d15:d8 ad7:ad0 intr , dreq i oh = C8 ma v 3.7 low-level output voltage i ol = 100 m av 0.2 v ol i ol = 8 ma v 0.4 high-level input current v ih = v cc5 m a 10 0.01 i ih note 2 low-level input current v il = v ss m a C0.01 C10 i il 3-state output leakage current v oh = v cc5 m a 10 0.01 i ozh d15:d8 ad7:ad0 v ol = v ss m a C0.01 C10 i ozl power supply current (operating) ma i cc3 v cc3 power supply current (standby) note 3 m a i ccs3 v cc3 50 50 ma i cc5 v cc5 note 3 m a i ccs5 v cc5 5 50 notes: 1. applied to d15:d8, ad7:ad0, a7:a0, cs , rd , wr , dack, ale, and adsel. the dc characteristics (1) applies to xin. 2. applied to a7:a0, cs , rd , wr , dack, ale, and adsel. the dc characteristics (1) applies to xin. 3. the xin pin is fixed to high level or low level in the suspend state. all the output pins are open.
ml60851a ? semiconductor 24/44 dc characteristics (3) usb port parameter condition applicable pin differential input sensitivity (d+) C (dC) unit v max. typ. min. 0.2 (v cc3 = 3.0 to 3.6 v, v ss = 0 v, ta = 0 to 70c) symbol v di d+, dC differential common mode range includes v di range v 2.5 0.8 v cm single ended receiver threshold v 2.0 0.8 v se high-level output voltage rl of 15 k w to v ss v 3.6 2.8 v oh low-level output voltage rl of 1.5 k w to 3.6 v v 0.3 v ol output leakage current 0 v < v in < 3.3 v m a +10 C10 i lo ac characteristics usb port parameter condition (notes 1. and 2.) applicable pin rise transition time cl = 50 pf unit ns max. typ. min. 4 (v cc3 = 3.0 to 3.6 v, v ss = 0 v, ta = 0 to 70c) symbol t r d+, dC fall transition time cl = 50 pf ns 25 4 t f rise/fall time matching % 140 90 t rfm output signal crossover voltage v 2 1.2 v crs driver output resistance steady state driver w 43 z drv data rate ava. bit rate (12 mb/s 0.25%) mbs 12.03 11.97 t drate 25 (t r /t f ) 28 notes: 1. 1.5 k w pull-up to 2.8 v on the d+ data line. 2. measured from 10% to 90% of the data signal.
ml60851a ? semiconductor 25/44 timing diagram read timing (1) (address separate adsel = 0) parameter symbol condition note address setup time ( rd )t 1 address ( cs ) hold time t 2 read data delay time t 3 read data hold time t 4 unit ns ns ns ns max. min. 21 25 0 recovery time t 5 ns fifo access time t 6 ns load 20 pf fifo read fifo read 0 63 42 5 2 1 3 4 ( rd ) address setup time ( cs )t 1 ns 10 5 ( cs ) a7:a0 cs rd ad7:ad0 t 1 t 6 t 2 t 3 t 4 t 5 data out notes: 1. t 1 and t 3 are defined depending upon cs or rd which becomes active last. 2. t 2 is defined depending upon cs or rd which becomes active first. 3. 3-clock time of oscillation clock (clock period: 21 ns). it is required for increment of fifo. 4. 2-clock time of oscillation clock (clock period: 21 ns). it is required for increment of fifo. 5. either of them should be met.
ml60851a ? semiconductor 26/44 read timing (2) (address/data multiplex adsel = 1) parameter symbol condition note address ( cs ) setup time t 1 address ( cs ) hold time t 2 read data delay time t 3 read data hold time t 4 unit ns ns ns ns max. min. 10 25 0 recovery time t 5 ns fifo access time t 6 ns load 20 pf fifo read fifo read 0 63 42 1 2 notes: 1. 3-clock time of oscillation clock (clock period: 21 ns). it is required for increment of fifo. 2. 2-clock time of oscillation clock (clock period: 21 ns). it is required for increment of fifo. ad7:ad0 ale cs rd t 2 t 4 data out address t 5 t 3 t 6 t 1
ml60851a ? semiconductor 27/44 write timing (1) (address separate adsel = 0) notes: 1. t 1 is defined depending upon cs or wr which becomes active last. 2. 3-clock time of oscillation clock (clock period: 21 ns). it is required for increment of fifo. 3. 2-clock time of oscillation clock (clock period: 21 ns). it is required for increment of fifo. 4. either of them should be met. parameter symbol condition note address setup time ( wr )t 1 address ( cs ) hold time t 2 write data setup time t 4 write data hold time t 5 unit ns ns ns ns max. min. 21 30 5 recovery time t 6 ns fifo access time t 7 ns fifo write fifo write 0 63 42 2 3 cs setup time t 3 ns 10 4 ( wr ) address setup time ( cs )t 1 ns 10 4 ( cs ) cs wr data in a7:a0 ad7:ad0 t 7 t 2 t 6 t 5 t 3 t 4 t 1
ml60851a ? semiconductor 28/44 write timing (2) (address/data multiplex adsel = 1) notes: 1. 3-clock time of oscillation clock (clock period: 21 ns). it is required for increment of fifo. 2. 2-clock time of oscillation clock (clock period: 21 ns). it is required for increment of fifo. parameter symbol condition note address ( cs ) setup time t 1 address ( cs ) hold time t 2 write data setup time t 3 write data hold time t 4 unit ns ns ns ns max. min. 10 30 5 recovery time t 5 ns fifo access time t 6 ns fifo write fifo write 0 63 42 1 2 ad7:ad0 address data in ale cs wr t 2 t 4 t 3 t 5 t 6 t 1
ml60851a ? semiconductor 29/44 dma transfer timing (1) ml60851a to memory (single transfer, single address mode) parameter symbol condition note dreq disable time t 1 dreq enable time t 2 dack hold time t 3 read data delay time t 4 1 unit ns ns ns ns max. min. 20 0 25 data hold time t 5 ns recovery time t 6 2 ns 63 ns load 20 pf load 20 pf 8-bit dma 16-bit dma 0 105 63 3 notes: 1. when in single address mode, cs and a7:a0 are ignored. t 4 is defined depending on dack or rd which becomes active last. 2. 3-clock time of oscillation clock (clock period: 21 ns). 3. 5-clock time of oscillation clock (clock period: 21 ns). t 1 t 2 t 5 t 4 dreq dack rd dout t 3 t 6
ml60851a ? semiconductor 30/44 dma transfer timing (2) ml60851a to memory (single transfer, dual address mode) parameter symbol condition note dreq disable time t 1 dreq enable time t 2 read data delay time t 3 t 4 1 unit ns ns ns ns max. min. 20 25 data hold time recovery time t 5 2 ns ns 63 load 20 pf load 20 pf 8-bit dma 16-bit dma 0 105 63 3 notes: 1. when in dual address mode, the dack is ignored. t 3 is defined depending on cs or rd which becomes active last. a7:a0 specifies the fifo address. refer to read timing (1) for address setup time and address hold time. 2. 3-clock time of oscillation clock (clock period: 21 ns). 3. 5-clock time of oscillation clock (clock period: 21 ns). t 2 t 4 t 3 t 1 a7:a0 dreq cs rd dout t 5
ml60851a ? semiconductor 31/44 dma transfer timing (3) ml60851a to memory (demand transfer, single address mode) parameter symbol condition note dreq disable time t 1 dack hold time t 2 read data delay time t 3 t 4 1 unit ns ns ns ns max. min. 0 25 data hold time recovery time t 5 2 ns ns 63 load 20 pf load 20 pf 8-bit dma 16-bit dma 20 0 105 3 notes: 1. w hen in single address mode, t 3 is defined depending on dack or rd which becomes active last. a7:a0 and cs are ignored. 2. 3-clock time of oscillation clock (clock period: 21 ns). 3. 5-clock time of oscillation clock (clock period: 21 ns). t 3 t 1 t 2 last packet read dreq dack rd dout t 5 t 4
ml60851a ? semiconductor 32/44 dma transfer timing (4) ml60851a to memory (demand transfer, dual address mode) parameter symbol condition note dreq disable time t 1 cs hold time t 2 read data delay time t 3 t 4 1 unit ns ns ns ns max. min. 25 data hold time recovery time t 5 2 ns ns load 20 pf load 20 pf 8-bit dma 16-bit dma 0 0 63 105 20 3 notes: 1. when in dual address mode, the dack is ignored. t 3 is defined depending on cs or rd which becomes active last. a7:a0 specifies the fifo address. refer to read timing (1) for address setup time and address hold time. 2. 3-clock time of oscillation clock (clock period: 21 ns). 3. 5-clock time of oscillation clock (clock period: 21 ns). a7:a0 dreq cs rd dout t 3 t 4 t 2 t 1 last packet read t 5
ml60851a ? semiconductor 33/44 dma transfer timing (5) memory to ml60851a (single transfer, single address mode) notes: 1. when in single address mode, cs and a7:a0 are ignored. 2. 3-clock time of oscillation clock (clock period: 21 ns). 3. 5-clock time of oscillation clock (clock period: 21 ns). t 1 t 3 t 5 t 7 t 6 t 2 dreq dack wr din t 4 parameter symbol condition note dreq disable time t 1 dreq enable time t 2 dack hold time write data setup time t 4 unit ns ns ns ns max. min. 20 0 write data hold time t 5 ns fifo access time t 3 ns t 6 load 20 pf 30 5 42 63 1 recovery time ns t 7 ns 63 105 8-bit dma 16-bit dma 2 3 fifo write
ml60851a ? semiconductor 34/44 dma transfer timing (6) memory to ml60851a (single transfer, dual address mode) parameter symbol condition note dreq disable time t 1 dreq enable time t 2 write data setup time unit ns ns ns max. min. 20 write data hold time t 4 ns fifo access time t 3 ns t 5 recovery time ns t 6 ns load 20 pf 63 30 5 42 63 105 2 3 8-bit dma 16-bit dma 1 fifo write t 2 t 1 t 3 t 4 t 5 a7:a0 dreq cs wr din t 6 notes: 1. when in dual address mode, the dack is ignored. refer to write timing (1) for address setup time and address hold time. 2. 3-clock time of oscillation clock (clock period: 21 ns). 3. 5-clock time of oscillation clock (clock period: 21 ns).
ml60851a ? semiconductor 35/44 dma transfer timing (7) memory to ml60851a (demand transfer, single address mode) parameter symbol condition note dreq disable time t 1 t 2 dack hold time write data setup time t 4 unit ns ns ns max. min. 20 42 write data hold time t 5 ns fifo access time t 3 ns recovery time t 6 ns ns load 20 pf 8-bit dma 16-bit dma 0 30 5 63 105 1 2 3 fifo write notes: 1. when in single address mode, a7:a0 and cs and ignored. 2. 3-clock time of oscillation clock (clock period: 21 ns). 3. 5-clock time of oscillation clock (clock period: 21 ns). t 1 t 3 last packet write t 4 t 2 dreq dack wr din t 5 t 6 (note) (note) the last write to reach the byte size (maximum packet size) specified by the ep1 payload register. to terminate dma transfer before reaching the maximum packet size, set ep1 packet ready by writing "1" to the ep1 transmit packet ready bit.
ml60851a ? semiconductor 36/44 dma transfer timing (8) memory to ml60851a (demand transfer, dual address mode) parameter symbol condition note dreq disable time t 1 t 2 cs hold time write data setup time t 4 unit ns ns ns max. min. 20 write data hold time t 5 ns fifo access time t 3 ns recovery time t 6 ns ns load 20 pf 8-bit dma 16-bit dma 0 30 5 42 63 105 1 2 3 fifo write notes: 1. when in dual address mode, the dack is ignored. a7:a0 specifies the fifo address. refer to write timing (1) for address setup time and address hold time. 2. 3-clock time of oscillation clock (clock period: 21 ns). 3. 5-clock time of oscillation clock (clock period: 21 ns). t 1 t 3 t 2 t 4 last packet write a7:a0 dreq cs wr din t 5 t 6 ( note ) refer to the p revious p a g e. (note)
ml60851a ? semiconductor 37/44 functional descriptions pin functional description usb interface crystal oscillator interface description assertion type i signal xin for internal oscillation, connect a crystal to xin and xout. o xout for external oscillation, supply an external 48 mhz clock signal to xin. set xout to be open. description assertion type i/o signal d+ usb data (plus). this signal and the dC signal are the transmitted or received data from/to usb bus. the table below shows values and results for these signal. d+ dC result 0 0 single end 0 0 1 differential "0" 1 0 differential "1" 1 1 undefined i/o dC usb data (minus). this signal and the d+ signal are the transmitted or received data from/to usb bus. the table above shows values and results for these signals.
ml60851a ? semiconductor 38/44 application interface note: 1. initial value immediately after resetting. its assertion can be changed by programming. description assertion type i/o signal d15:d8 upper byte (msb) of data bus. this data bus is used by applications to access register files and fifo data. i/o ad7:ad0 lower byte (lsb) of data bus when adsel is low. address and lower byte of data bus are multiplexed when adsel is high. i a7:a0 address when adsel is low. this address signal is used by application to access register files and fifo data. this signal is ignored (all lows or all highs) when adsel is high. low i cs chip select. when this signal is asserted low, the ml60851a is selected and ready to read or write data. low i rd read strobe. when this signal is asserted low, the read instruction is executed. low i wr write strobe. when this signal is asserted low, the write instruction is executed. low (note 1) o intr interrupt request. when this signal is asserted, the ml60851a makes an interrupt request to the application. low (note 1) o dreq dma request. this signal requests the endpoint fifo to make a dma transfer. high (note 1) i dack dma acknowledge signal. this signal, when asserted, enables accessing fifos, without address bus setting. i ale when adsel is high, the address and cs on ad7:ad0 is latched at the trailing edge of this signal. this signal is ignored when adsel is low. i adsel when adsel is low, the address is input on a7:a0 and data i input on d15:d8 and ad7:ad0. when adsel is high, the lower bytes (lsb) of address and data are multiplexed on ad7:ad0. i reset system reset. when this signal is asserted low, the ml60851a is reset. when the ml60851a is powered on, this signal must be asserted for 1 m s. low
ml60851a ? semiconductor 39/44 functional description the ml60851a usb device controller contains the protocol engine, dpll, timer, status/control, fifo control, application interface, and remote wakeup blocks. ? protocol engine the protocol engine handles the usb communication protocol. it performs control of packet transmission/reception, generation/detection of synchronous patterns, crc generation/checking, nrzi data modulation, bit stuffing, and packet id (pid) generation/checking. ? dpll (digital phase locked loop) the dpll extracts clock and data from the usb differential received data (d+ and dC). ? timer the timer block monitors idle time on the usb bus. ? status/control the status control block moniors the transaction status and transmits control events to the application through an interrupt request.
ml60851a ? semiconductor 40/44 ? fifo control the fifo control block controls all fifo operations for transmitting and receiving usb packets. the fifo configuration is described below. endpoint fifo/8-byte setup register configuration endpoint address program size fifo type reception transmission transmission reception/transmission 0 0 1 3 8 bytes 8 bytes 8 bytes 64 bytes (2 levels) function transfer control transfer control bulk-in and bulk-out interrupt reception/transmission 2 64 bytes bulk-out and bulk-in every fifo has a flag that indicates a full or empty fifo and the capability of re-transmitting and re-receiving data. endpoint addresses 1 and 2 can be used for either of reception and transmission by writing the register. the fifo at endpoint address 1 can be used for dma transfer. for control transfer setup ready packet ready packet ready for bulk transfer packet ready dma request packet ready 64-byte fifo 64-byte fifo 8-byte fifo 8-byte fifo tx 8-byte fifo rx 8-byte setup register endpoint address 0 endpoint address 0 endpoint address 0 endpoint address 1 endpoint address 3 ep0 receive fifo ep0 transmit fifo ep1 fifo (128 bytes) (selectable for transmitter or receiver) ep3 fifo (8 bytes) packet ready 64-byte fifo endpoint address 2 ep2 fifo (64 bytes) (selectable for transmitter or receiver)
ml60851a ? semiconductor 41/44 ? interrupt interrupt factors include packet ready for a transmit/receive fifo, setup ready for 8-byte setup data, and suspend. generation of each interrupt request can be enabled or disabled by the interrupt enable register. ?dma 8-bit and 16-bit demand transfer dma and single transfer dma are enabled for bulk-transfer fifo at endpoint address 1. in demand transfer mode, dreq is asserted when a valid packet arrives at the fifo. when the external dma contoller has completed transferring all byte data of a received packet, dreq is deasserted. accordingly, other devices cannot access the local bus during dma transfer. in single tranfer mode, each time transfer of one byte data is completed, dreq is deasserted. while dreq is deasserted, other devices can access the local bus. ? remote wakeup this functional block supports the remote wakeup function. ? usb transfers the ml60851a supports the two transfer types (control transfer and bulk transfer) of four transfer types (control, isochronous, interrupt, and bulk) defined by the usb specifications. - the control transfer is required for transfer of configuration, commands, and status information between the host and devices. - the bulk transfer enables transfer of a large amount of data when the bus bandwidth is enough. ? usb transceiver the ml60851a contains an oki's usb transceiver which converts internal unidirectional signals into usb-compatible signals. this enables the designer's application module to interface to the physical layer of the usb.
ml60851a ? semiconductor 42/44 example of oscillator circuit ml60851a rf c3 c2 l1 xin xout crystal: hc-49u (kinseki, ltd) c2 = 5 pf c3 = 1000 pf rf = 1 m w l1 = 2.2 m f note: the example indicated above is not guaranteed for circuit operation.
ml60851a ? semiconductor 43/44 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.41 typ. qfp44-p-910-0.80-2k mirror finish
ml60851a ? semiconductor 44/44 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tqfp44-p-1010-0.80-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.28 typ. mirror finish
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1998 oki electric industry co., ltd. printed in japan e2y0002-28-41

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